RISC-V is emerging as a potentially biggest competitor to ARM-based world of microprocessors. Its open nature allows the designers to change features of the processor but still retaining compatibility with the already accepted instruction set architecture (ISA). There are a number of open implementations of RISC-V specified in traditional HDLs (Verilog, VHDL) or by using new specification paradigms (e.g. Spinal, Chisel).
The project explores how the extensions to RISC-V processor can be efficiently made to match the requirements of specific applications, looking to two aspects: (1) hardware and architectural extensions including the instruction set and (2) software compatibility with existing tools and programming languages. As specific use case we use a novel programming paradigm called SystemGALS that may benefit from customisation of the target processor, in our case RISC-V.
Undergraduate
Extension of processor instruction set including the extensions of its datapath for execution of new instructions
Creation of synthesisable model of extended RISC-V, RISC-VExt
Analysis of SystemGALS language and identification of constructs susceptible for new instructions
Exploration of SystemGALS compiler and its modifications to match new ISA
Good knowledge of computer architecture, digital design, using hardware description languages and willingness to understand new programming paradigms for concurrent systems development.
Lab allocations have not been finalised